Programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) include configurable logic blocks and memory blocks. As will be appreciated by those skilled in the art, the FPGA architecture can be configured by appropriately setting configuration bits. In general, the configuration bits control connections between available routings within the FPGA. By appropriately setting a particular combination of configuration bits, the programmable architecture of the FPGA can be connected, i.e., programmed, to provide a particular functionality. It should be appreciated that by setting different, yet appropriate, combinations of the configuration bits, the FPGA can be connected to provide different functionality. Hence, in some FPGA architectures, the configurable memory blocks can be configured into a number of different memory types and sizes. A FPGA programmer can select the particular memory type and size that best suits the needs of the system to be defined on the FPGA. Therefore, it is desirable to provide an FPGA architecture that supports a broad spectrum of memory block configuration options.